Semiconductor device

ABSTRACT

The present invention provides a semiconductor device that ensures both the breakdown voltage characteristic and specific on-resistance characteristic required for a high-voltage semiconductor device and that includes a gate over a substrate, a source region formed at one side of the gate, a drain region formed at the other side of the gate, and a plurality of device isolation films formed between the source region and the drain region, below the gate.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No.10-2012-0096623, filed on Aug. 31, 2012, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Field

Exemplary embodiments of the present invention relate to semiconductordevice fabrication technology, and, more particularly, to a high-voltageMOS transistor.

2. Description of the Related Art

A laterally double-diffused MOS (LDMOS) transistor that is a highvoltage MOS transistor is advantageous over a bipolar transistor,because the LDMOS transistor has a high input impedance and power gain,and a circuit for driving the same is very simple. In addition, becausethe LDMOS transistor is a unipolar device, it is advantageous that theLDMOS transistor is free from the delay caused by minority carrierrecombination in a turn-off operation. For these reasons, the LDMOStransistor is widely used in various power devices, including integratedcircuits (ICs), power converters, motor controllers and automotive powerdevices.

FIG. 1 is a cross-sectional view showing a laterally double-diffused MOS(LDMOS) transistor according to the prior art. FIG. 1 illustrates astructure in which two N-channel lateral double-diffused MOS transistorsare disposed symmetrically with respect to a bulk pick-up region on asubstrate.

Referring to FIG. 1, the N-channel lateral double-diffused MOStransistor according to the prior art includes an N-type deep well 12formed on a P-type substrate 11, both an N-well 14 and P-well 16 formedin the N-type deep well 12, both an N-type source region 17 and a P-typebulk pick-up region 18 formed in the P-well 16, an N-type drain region15 formed in the N-type well 14, a gate electrode 20 formed over thesubstrate 11 between the end of the N-type source region 17 and beforethe N-type drain region 15, and an insulating layer 21 interposedbetween the gate electrode 20 and the P-type substrate 11. Herein, theinsulating layer 21 includes a gate insulating film 19 and a field oxidefilm 13.

As it is well known in the art, a process of designing a high-voltageMOS transistor basically requires the minimization of the specificon-resistance (Rsp) of the transistor while maintaining the breakdownvoltage (BV) at a high level.

Methods used to increase the breakdown voltage (BV) of the high-voltageMOS transistor in the prior art include reducing the impurity dopingconcentration of an impurity region (e.g., N-type deep well 12)corresponding to a drift region D, increasing the length of the fieldoxide film 13 to increase the length of the drift region D, orintroducing a P-type impurity layer into the N-type deep well 12corresponding to the drift region D. For reference, a region in whichthe gate electrode 20 overlaps with the P-well 16 acts as the channelregion C, and a region ranging from the end of the channel region C tothe drain region 15 is referred to as the drift region D.

However, the above-described methods inevitably involve an increase inthe specific on-resistance (Rsp) of the N-channel lateraldouble-diffused MOS transistor, thereby reducing the specific on-currentof the transistor. On the contrary, to decrease the specificon-resistance of the transistor, when the impurity doping concentrationof an impurity region corresponding to the drift region D is increasedor the length of the drift region D is reduced, the breakdown voltage(BV) characteristic of the transistor will be deteriorated.

As described above, the breakdown voltage (BV) characteristic and thespecific on-resistance (Rsp) characteristic have a trade-offrelationship. Thus, there is an urgent need for a method that maysustain both the breakdown voltage (BV) and specific on-resistance (Rsp)characteristics required for a high-voltage MOS transistor.

SUMMARY

Exemplary embodiments of the present invention are directed to asemiconductor device that may sustain both the breakdown voltage andspecific on-resistance characteristics required for a high-voltage MOStransistor.

In accordance with an exemplary embodiment of the present invention, asemiconductor device may include a gate formed over a substrate, asource region formed at one side of the gate, a drain region formed atthe other side of the gate, and a plurality of device isolation filmsformed between the source region and the drain region, below the gate.

In accordance with another exemplary embodiment of the presentinvention, a semiconductor device may include a second-conductivity-typedeep well formed over a substrate, a first-conductivity-type well formedin the second-conductivity-type deep well, a gate formed over thesubstrate so as to partially overlap with the first-conductivity-typewell, a second-conductivity-type source region formed in thefirst-conductivity-type well, at one side of the gate, asecond-conductivity-type drain region in the second-conductivity-typedeep well, at the other side of the gate, and a plurality of deviceisolation films formed in the second-conductivity-type deep well, belowthe gate.

In accordance with another exemplary embodiment of the presentinvention, a semiconductor device may include a first-conductivity-typesubstrate, a first-conductivity-type first well andsecond-conductivity-type second well formed over thefirst-conductivity-type substrate, a gate formed over thefirst-conductivity-type substrate so as to overlap with thefirst-conductivity-type first well and the second-conductivity-typesecond well, a second-conductivity-type source region formed in thefirst-conductivity-type first well, at one side of the gate, asecond-conductivity-type drain region formed in thesecond-conductivity-type second well, at the other side of the gate, anda plurality of device isolation films formed in thesecond-conductivity-type second well, below the gate.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view showing a lateral double-diffused MOStransistor according to the prior art.

FIG. 2 is a cross-sectional view showing a lateral double-diffused MOStransistor according to a first exemplary embodiment of the presentinvention.

FIG. 3 is a cross-sectional view showing a laterally double-diffused MOStransistor according to a second exemplary embodiment of the presentinvention.

FIGS. 4A to 4E are cross-sectional views showing a method forfabricating a lateral double-diffused MOS transistor according to anexemplary embodiment of the present invention.

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as limited to the embodiments set forth herein. Rather, theseembodiments are provided so that this disclosure will be thorough andcomplete, fully conveying the scope of the present invention to thoseskilled in the art. Throughout the disclosure, like reference numeralsrefer to like parts throughout the various figures and embodiments ofthe present invention.

The drawings are not necessarily to scale and, in some instances,proportions may have been exaggerated in order to clearly Illustratefeatures of the embodiments. It should be readily understood that themeaning of “on” and “over” in the present disclosure should beinterpreted in the broadest manner such that “on” means not only“directly on” but also “on” something with an intermediate feature(s) ora layer(s) therebetween, and that “over” means not only directly on topbut also on top of something with an intermediate feature(s) or alayer(s) therebetween. It is also noted that in this specification,“connected/coupled” refers to one component not only directly couplinganother component but also indirectly coupling another component throughan intermediate component. In addition, a singular form may include aplural form as long as it is not specifically mentioned in a sentence.

The following exemplary embodiments of the present invention provide asemiconductor device that may sustain both the breakdown voltage (BV)and specific on-resistance (Rsp) characteristics required for ahigh-voltage MOS transistor. The semiconductor device according to theembodiments of the present invention is characterized as a deviceisolation film overlapping a gate electrode that is divided into aplurality of portions so that the E-field between the gate electrode andthe drain region is induced to increase the breakdown voltage of thedevice while an accumulation layer is induced between the plurality ofdevice isolation films to decrease the specific on-resistance (Rsp) ofthe device.

Hereinafter, a description will be made by an example of an N-channellateral double-diffused MOS (LDMOS) transistor to which the feature ofthe present invention has been applied. Thus, in the followingdescription, a first conductivity type corresponds to a P type, and asecond conductivity type corresponds to an N type. In the case of thefeature of the present invention being applied to a P-channel lateraldouble-diffused MOS transistor, a first conductivity type corresponds toan N type, and a second conductivity type corresponds to a P type.

FIG. 2 is a cross-sectional view showing a lateral double-diffused MOStransistor according to a first exemplary embodiment of the presentinvention. FIG. 2 illustrates a structure in which two N-channel lateraldouble-diffused MOS transistors are disposed symmetrically with respectto a bulk pick-up region on a substrate.

As shown in FIG. 2, a lateral double-diffused MOS transistor accordingto a first exemplary embodiment of the present invention includes asecond-conductivity-type deep well 103 and a second-conductivity-typeburied impurity layer 102 formed over a substrate 101, afirst-conductivity-type first well 104 formed in thesecond-conductivity-type deep well 103, a couple ofsecond-conductivity-type source regions 109 and afirst-conductivity-type bulk pick-up region 110 formed in thefirst-conductivity-type first well 104, a second-conductivity-typesecond well 105 formed in the second-conductivity-type deep well 103, asecond-conductivity-type drain region 111 formed in thesecond-conductivity-type second well 105, a gate G formed on thesubstrate 101, and a plurality of device isolation films 112 and 113below the gate G formed in the second-conductivity-type deep well 103.Herein, a region where the first-conductivity-type first well 104overlaps the gate G acts as a channel region C, and a region rangingfrom the sidewall of the first-conductivity-type first well 104 belowthe gate G in the second-conductivity-type deep well 103 to thesecond-conductivity-type drain region 111 is referred to as a driftregion D.

The substrate 101 may include single crystalline silicon. Thus, thesubstrate 101 may be a SOI (silicon-on-insulator) substrate consistingof a bulk silicon substrate or support substrate, a buried insulatinglayer, and an epitaxial layer (e.g., epitaxial silicon layer), allsequentially deposited in that order. Alternatively, the substrate 101may be a substrate doped with a first-conductivity-type impurity.

The second-conductivity-type deep well 103 may have an impurity dopingconcentration lower than those of the first-conductivity-type well 104,the second-conductivity-type second well 105, or thesecond-conductivity-type buried impurity layer 102 to improve thebreakdown voltage characteristic of the device. Thus, when the impuritydoping concentration of the second-conductivity-type deep well 103 isreduced in such a manner that the specific on-resistance characteristicof the device is not deteriorated, the breakdown voltage characteristicof the device may be improved.

The second-conductivity-type buried impurity layer 102 is located underthe second-conductivity-type deep well 103 and serves to prevent adepletion region from extending excessively from thefirst-conductivity-type first well 104 the second-conductivity-typesecond well 105 in the substantially perpendicular direction withrespect to the length of the substrate 101, thereby improving thebreakdown voltage characteristic of the device. For this purpose, theimpurity doping concentration of the second-conductivity-type buriedimpurity layer 102 may be higher than those of thesecond-conductivity-type deep well 103, the first-conductivity-typefirst well 104 or the second-conductivity-type second well 105.

The first-conductivity-type first well 104 and thesecond-conductivity-type second well 105 are spaced at a predeterminedinterval from each other in the horizontal direction with respect to thelength of the substrate 101. Herein, the interval between thefirst-conductivity-type first well 104 and the second-conductivity-typesecond well 105 may correspond to the length of the drift region D. Theimpurity doping concentrations of the first-conductivity-type first well104 or the second-conductivity-type second well 105 may be higher thanthat of the second-conductivity-type deep well 103.

The gate G formed over the substrate 101 may be a stack of a gateinsulating film 106 and a gate electrode 107. The gate insulating film106 may be any one selected from the group consisting of an oxide film,a nitride film, an oxynitride film, and stacks thereof. The thickness ofthe gate insulating film 106 may be controlled by an operating voltage.The gate electrode 107 may include a semiconductor film such as asilicon film or a silicon-germanium film, and/or a metallic film such asa metal film, a metal oxide film, a metal nitride film or a metalsilicide film. In addition, a spacer 108 is formed on the side wall ofthe gate G. The spacer 108 includes an insulating film.

The couple of second-conductivity-type source regions 109 are formed inthe first-conductivity-type first well 104 so as to be aligned with oneside of the gate G, and the first-conductivity-type bulk pick-up region110 is formed between the second-conductivity-type source regions 109 inthe first-conductivity-type first well 104. Eachsecond-conductivity-type source region 109 may have a lightly dopeddrain (LDD) structure, and the first-conductivity-type bulk pick-upregion 110 may have an impurity doping concentration higher than thefirst well 104. The second-conductivity-type drain region 111 is formedat a distance from the other side of the gate G, and thesecond-conductivity-type drain region 111 is formed in thesecond-conductivity-type second well 105. The impurity dopingconcentration of the second-conductivity-type drain region 111 may behigher than that of the second-conductivity-type second well 105.

The plurality of device isolation films 112 and 113 is formed in thesecond-conductivity-type deep well 103 with distance from each other andbelow the gate G. Each of the device isolation films 112 and 113 mayinclude a structure formed by a shallow trench isolation (STI) process.The structure formed by the STI process has an advantage that the depth,linewidth and spacing may be easily controlled compared to a field oxidefilm formed by a LOCOS (local oxidation of silicon) process according tothe prior art. Thus, when the STI process is used, the plurality ofdevice isolation films 112 and 113 may be more effectively formed in alimited space compared to a field oxide film formed by the LOCOSprocess.

The device isolation film 112, alternatively referred to as a firstdevice isolation film 112, and the device isolation film 113,alternatively referred to as a second device isolation film 113, may bedisposed at predetermined intervals from each other in the horizontaldirection with respect to the length of the substrate 101. Among theplurality of device isolation films 112 and 113, the first deviceisolation film 112 disposed closest to the second-conductivity-typedrain region 111 is formed in contact with the second-conductivity-typedrain region 111. Thus, the first device isolation film 112 formed incontact with the second-conductivity-type drain region 111 may overlapwith a portion of the gate G. Herein, the first device isolation film112 formed in contact with the second-conductivity-type drain region 111is preferably formed to have the larger linewidth and depth among theplurality of device isolation films 112 and 113. This improves thebreakdown voltage characteristic of the device while dispersing anelectric field because the part of the gate insulating film 106 formedover the second-conductivity-type deep well 103 between the first deviceisolation film 112 and the second device isolation film 113 may resistthe set breakdown voltage.

The plurality of device isolation films 112 and 113 may have the samelinewidth, or the linewidth thereof may decrease gradually in accordancewith the direction from the second-conductivity-type drain region 111toward the second-conductivity-type source region 109. Specifically, thefirst device isolation film 112 and the second device isolation film 113have a first linewidth CD1 and a second linewidth CD2, respectively, inwhich the first linewidth CD1 and the second linewidth CD2 may be thesame, or the second linewidth CD2 may be shorter than the firstlinewidth CD1.

The plurality of device isolation films 112 and 113 may have a depthgreater than the second-conductivity-type source region 109 and greaterthan the second-conductivity-type drain region 111 with respect to thesurface of the substrate 101. The plurality of device isolation films112 and 113 may have a depth less than the first-conductivity-type firstwell 104 and less than the second-conductivity-type second well 105.Also, the plurality of device isolation films 112 and 113 may have thesame depth as or the depth thereof may decrease gradually in accordancewith the direction from the second-conductivity-type drain region 111toward the second-conductivity-type source region 109. Specifically, thefirst device isolation film 112 and the second device isolation film 113have a first depth D1 and a second depth D2, respectively, in which thedepth of the first depth D1 and the second depth D2 may be the same, orthe depth of the second depth D2 may be shorter than that of the firstdepth D1.

According to the above-described first exemplary embodiment of thepresent invention, the plurality of device isolation films 112 and 113are formed below the gate G in the second-conductivity-type deep well103 and thus the breakdown voltage characteristic and specificon-resistance characteristic of the device may be simultaneouslyimproved.

Hereinafter, detailed description will be made on the principle of thepresent invention in which the breakdown voltage characteristic andspecific on-resistance characteristic of the device may besimultaneously improved by forming the plurality of device isolationfilms 112 and 113.

In the present invention, breakdown voltage refers to a voltage measuredbetween the second-conductivity-type drain region 111 and thesecond-conductivity-type source region 109 that is in a state in which ahigh voltage is applied to the second-conductivity-type drain region 111and a ground voltage is applied to the gate G. Due to the high voltageapplied to the second-conductivity-type drain region 111, a deletionregion extends from the second-conductivity-type drain region 111, whilean E-field increases. In the prior art as shown in FIG. 1, because onefield oxide film (or device isolation film) was formed between theN-type drain region 15 and the N-type source region 17, the generatedE-field was concentrated on the N-type source region 17 from the drainregion 15, thereby deteriorating the breakdown voltage characteristic ofthe device.

However, in the embodiment of the present invention, an E-field isformed between the second-conductivity-type drain region 111 and theportion of the gate G that is formed adjacent to thesecond-conductivity-type deep well 103 between the plurality of deviceisolation films 112 and 113. Thus, the E-field generated between thesecond-conductivity-type drain region 111 and the gate G may relieve theE-field caused by a depletion region extending from thesecond-conductivity-type drain region 111, thereby dispersing thegenerated E-field that is concentrated on the second-conductivity-typesource region 109 to the second-conductivity-type drain region 111,thereby improving the breakdown voltage characteristic of the device.

Accordingly, the breakdown voltage characteristic of the device may beimproved without reducing the impurity doping concentration of animpurity region (e.g., second-conductivity-type deep well 103)corresponding to the drift region D, unlike the prior art. Thus, thespecific on-resistance characteristic of the device due to a decrease inthe impurity doping concentration of the second-conductivity-type deepwell 103 may be prevented from deteriorating. In addition, the breakdownvoltage characteristic of the device may be improved without increasingthe length of the drift region D (i.e., without increasing the length ofa field oxide film or device isolation film). Thus, the current path maybe prevented from increasing that may be due to an increase in thelength of the drift region D, thereby preventing deterioration in thespecific on-resistance characteristic. In addition, the breakdownvoltage characteristic of the device may be improved by introducing animpurity layer with a different conductivity type into an impurityregion (e.g., second-conductivity-type deep well 103) corresponding tothe drift region D. Thus, the number of process steps may be reduced bycontrolling the introduction of the impurity layer, and the specificon-resistance characteristic may be prevented from deteriorating that iscaused by a potential barrier between the deep well 103 and the impuritylayer that may have different conductivity types.

When a bias is applied to the gate G, a channel caused by an inversionlayer is formed on the surface of the first-conductivity-type first well104 overlapping the gate G, and an accumulation layer is formed on thesurface of the second-conductivity-type deep well 103, overlapping thegate G and the surface of the plurality of device isolation films 112and 113. Herein, the inversion layer and the accumulation layer act ascurrent paths between the second-conductivity-type source region 109 andthe second-conductivity-type drain region 111.

In the prior art as shown in FIG. 1, the current path by theaccumulation between the N-type drain region 15 and the N-type sourceregion 17 was formed as a planar structure along the bottom of the fieldoxide film. However, in the present invention, the plurality of deviceisolation films 112 and 113 exhibit the effect of widening the currentpath caused by the accumulation layer. Specifically, because the portionof the second-conductivity-type deep well 103 between the plurality ofdevice isolation films 112 and 113 comes into contact with the gateinsulation film 106, a portion of the accumulation layer with aconductivity higher than that of a portion of the accumulation layerformed on the surface of the plurality of device isolation films 112 and113 but below the gate G is formed between the plurality of deviceisolation films 112 and 113 so that the current path caused by theaccumulation layer widens. Therefore, current transfer between thesecond-conductivity-type drain region 111 and thesecond-conductivity-type source region 109 is improved while thespecific on-resistance of the device decreases.

As a result, according to the present invention, the plurality of deviceisolation films 112 and 113 are formed below the gate G in thesecond-conductivity-type deep well 103 between thesecond-conductivity-type drain region 111 and thesecond-conductivity-type source region 109, and thus the breakdownvoltage characteristic of the device may be improved without having touse the prior art methods that inevitably involve an increase inspecific on-resistance. At the same time, the current path may bewidened by the plurality of device isolation films 112 and 113, therebyimproving the specific on-resistance characteristic of the device.

FIG. 3 is a cross-sectional view showing a lateral double-diffused MOStransistor according to a second embodiment of the present invention.FIG. 3 illustrates a structure in which two N-channel lateraldouble-diffused MOS transistors are disposed symmetrically with respectto a bulk pick-up region on a substrate.

As shown in FIG. 3, a lateral double-diffused MOS transistor accordingto a second exemplary embodiment of the present invention includes aburied impurity layer 202 formed on a first-conductivity-type substrate201, a first-conductivity-type first well 204 formed in thefirst-conductivity-type substrate 201, a couple ofsecond-conductivity-type source regions 209 and afirst-conductivity-type bulk pick-up region 210 formed in thefirst-conductivity-type first well 204, a second-conductivity-typesecond well 205 formed in the first-conductivity-type substrate 201, asecond-conductivity-type drain region 211 formed in thesecond-conductivity-type second well 205, a gate G formed on thefirst-conductivity-type substrate 201, and a plurality of deviceisolation films 212 and 213 below the gate G and in thesecond-conductivity-type second well 205. Herein, a region where thefirst-conductivity-type first well 204 overlaps the gate G acts as achannel region C, and a region ranging from the sidewall of thefirst-conductivity-type first well 204 below the gate G to thesecond-conductivity-type drain region 211 is referred to as a driftregion D.

The substrate 201 may include single crystalline silicon. Thus, thesubstrate 201 may be a SOI (silicon-on-insulator) substrate consistingof a bulk silicon substrate or support substrate, a buried insulatinglayer and an epitaxial layer (e.g., epitaxial silicon layer), allsequentially deposited in that order.

The buried impurity layer 202 is located on the first-conductivity-typesubstrate 201 and serves to prevent a depletion region from extendingexcessively from the first-conductivity-type first well 204 and thesecond-conductivity-type second well 205 in an upward diagonal directionwith respect to the length of the substrate 201, thereby improving thebreakdown voltage characteristic of the device.

The first-conductivity-type first well 204 and thesecond-conductivity-type second well 205 may be disposed at apredetermined distance from each other in the horizontal direction withrespect to the length of the substrate 201. Alternatively, they may alsobe disposed such that the sidewall of the first-conductivity-type firstwell 204 and the sidewall of the second-conductivity-type second well205, which face each other, are adjacent to each other. When thefirst-conductivity-type first well 204 and the second-conductivity-typesecond well 205 are formed at a predetermined distance from each otherin the horizontal direction with respect to the length of the substrate201, the breakdown voltage characteristic of the device may be improved.When the first-conductivity-type first well 204 and thesecond-conductivity-type second well 205 are formed adjacent to eachother, the specific on-resistance characteristic of the device may beimproved.

The gate G formed on the substrate 201 may be a stack of a gateinsulating film 206 and a gate electrode 207. The gate insulating film206 may be any one selected from the group consisting of an oxide film,a nitride film, an oxynitride film, and stacks thereof. The thickness ofthe gate insulating film 206 may be controlled by a operating voltage.The gate electrode 207 may include a semiconductor film such as asilicon film or a silicon-germanium film, and/or a metallic film such asa metal film, a metal oxide film, a metal nitride film or a metalsilicide film. In addition, a spacer 208 is formed on the sidewall ofthe gate G. The spacer 208 includes an insulating film.

The couple of second-conductivity-type source regions 209 are formed inthe first-conductivity-type first well 204 so as to be aligned with oneside of the gate G, and the first-conductivity-type bulk pick-up region210 is formed between the second-conductivity-type source regions 209 inthe first-conductivity-type first well 204. Eachsecond-conductivity-type source region 209 may have a lightly dopeddrain (LDD) structure, and the first-conductivity-type bulk pick-upregion 210 may have an impurity doping concentration higher than thefirst-conductivity-type first well 204.

The second-conductivity-type drain region 211 is formed at a distancefrom the other side of the gate G, and the second-conductivity-typedrain region 211 is formed in the second-conductivity-type second well205. The impurity doping concentration of the second-conductivity-typedrain region 211 may be higher than that of the second-conductivity-typesecond well 205.

The plurality of device isolation films 212 and 213 is formed in thesecond-conductivity-type second well 205 with distance from each otherand below the gate G. Each of the device isolation films 212 and 213 mayinclude a structure formed by an STI (shallow trench isolation) process.The structure formed by the STI process has an advantage that the depth,linewidth and spacing may be easily controlled compared to a field oxidefilm formed by a LOCOS (local oxidation of silicon) according to theprior art. Thus, when the STI process is used, the plurality of deviceisolation films 212 and 213 may be more effectively formed in a limitedspace compared to a field oxide film formed by the LOCOS process.

The device isolation film 212, alternatively referred to as a firstdevice isolation film 212, and the device isolation film 213,alternatively referred to as a second device isolation film 213, may bedisposed at predetermined intervals from each other in the horizontaldirection with respect to the length of the substrate 201. Among theplurality of device isolation films 212 and 213, the first deviceisolation film 212 disposed closest to the drain region 211 is formed incontact with the second-conductivity-type drain region 211. Thus, thefirst device isolation film 212 formed in contact with thesecond-conductivity-type drain region 211 may overlap with a portion ofthe gate G. Herein, the first device isolation film 212 formed incontact with the second-conductivity-type drain region 211 is preferablyformed to have the larger linewidth and depth among the plurality ofdevice isolation films 212 and 213. This improves the breakdown voltagecharacteristic of the device while dispersing an electric field becausethe part of the gate insulating film 206 formed over thesecond-conductivity-type deep well 205 between the first deviceisolation film 212 and the second device isolation film 213 may resistthe set breakdown voltage.

The plurality of device isolation films 212 and 213 may have the samelinewidth, or the linewidth thereof may decrease gradually in accordancewith the direction from the second-conductivity-type drain region 211toward the second-conductivity-type source region 209. Specifically, thefirst device isolation film 212 and the second device isolation film 213have a first linewidth CD1 and a second linewidth CD2, respectively, inwhich the first linewidth CD1 and the second linewidth CD2 may be thesame, or the second linewidth CD2 may be shorter than the firstlinewidth CD1.

The plurality of device isolation films 212 and 213 may have a depthgreater than the second-conductivity-type source region 209 and greaterthan the second-conductivity-type drain region 211 with respect to thesurface of the substrate 201. The plurality of device isolation films212 and 213 may have a depth less than the first-conductivity-type firstwell 204 and less than the second-conductivity-type second well 205.Also, the plurality of device isolation films 212 and 213 may have thesame depth as, or the depth thereof may decrease gradually in accordancewith the direction from the second-conductivity-type drain region 211toward the second-conductivity-type source region 209. Specifically, thefirst device isolation film 212 and the second device isolation film 213have a first depth D1 and a second depth D2, respectively, in which thedepth of the first depth D1 and the second depth D2 may be the same, orthe depth of the second depth D2 may be shorter than the first depth D1.

According to the above-described second exemplary embodiment of thepresent invention, the plurality of device isolation films 212 and 213are formed below the gate G in the second-conductivity-type second well205, and thus the breakdown voltage characteristic and specificon-resistance characteristic of the device may be simultaneouslyimproved.

FIGS. 4A to 4E are cross-sectional views showing a method forfabricating a lateral double-diffused MOS transistor according to oneembodiment of the present invention. Hereinafter, one embodiment of amethod for fabricating the lateral double-diffused MOS transistor havingthe structure shown in FIG. 2 will be described.

As shown in FIG. 4A, a substrate 31 is prepared. The substrate 31 mayinclude single crystalline silicon. Thus, the substrate 31 may be a bulksilicon substrate or a SOI (silicon-on-insulator) substrate. Thesubstrate 31 may be an undoped substrate or a substrate doped with afirst-conductivity-type impurity.

Then, a second-conductivity-type buried impurity layer 32 and asecond-impurity-type deep well 33 are sequentially formed on thesubstrate 31. They may be formed by an ion injection process in such amanner that the buried impurity layer 32 is located under the deep well33. The buried impurity layer 32 may be formed to have an impurityconcentration higher than that of the second-impurity-type deep well 33in order to improve the breakdown voltage characteristic of the device.

As shown in FIG. 4B, a first-conductivity-type first well 34 is formedin the second-impurity-type deep well 33. The first-conductivity-typefirst well 34 may be formed by a series of processes of forming a maskpattern (not shown) for opening regions that correspond to the sourceregion, bulk pick-up region and channel region of the lateraldouble-diffused MOS transistor, and then ion-injecting afirst-conductivity-type impurity, and removing the mask pattern.

Then, a second-conductivity-type second well 35 is formed in thesecond-impurity-type deep well 33. The second-conductivity-type seconddeep well 35 may be formed by a series of processes of forming a maskpattern (not shown) on the substrate 31 for opening a region thatcorresponds to the drain region of the lateral double-diffused MOStransistor and then, ion-injecting a second-conductivity-type impurity,and removing the mask pattern.

As shown in FIG. 4C, a plurality of device isolation films 36 and 37 areformed over the substrate 31 and is spaced at predetermined distancesfrom each other in the horizontal direction with respect to the lengthof the substrate 31. The plurality of device isolation films 36 and 37may be formed to have a depth less than that of thefirst-conductivity-type first well 34 and less than that of thesecond-conductivity-type second well 35. The plurality of deviceisolation films 36 and 37 may be formed by a STI (shallow trenchisolation) process. When the STI process is used, the depth, linewidthand spacing of the device isolation films may be easily controlled,compared to a field oxide film formed by a LOCOS (local oxidation ofsilicon) process according to the prior art.

The plurality of device isolation films 36 and 37 may be formed in anarea corresponding to the drift region of the lateral double-diffusedMOS transistor. The plurality of device isolation films 36 and 37 may beformed such that the device isolation films 36 and 37 may have the samelinewidth or the linewidth thereof may decrease gradually in accordancewith the direction from the second-conductivity-type second well 35toward the first-conductivity-type first well 34. In addition, theplurality of device isolation films 36 and 37 may be formed such thatthe device isolation films 36 and 37 may have the same depth or thedepth thereof may decrease gradually in accordance with the directionfrom the second-conductivity-type second well 35 toward thefirst-conductivity-type first well 34.

As shown in FIG. 4D, a gate insulating film 38 and a gate conductivefilm are sequentially formed on the entire surface of the substrate 31,and then patterned to form a gate G consisting of a stack of a gateinsulating film 38 and a gate electrode 39.

The gate G may be formed such that one end of the gate G overlaps with aportion of the first-conductivity-type first well 34 and the other endthereof is spaced at a predetermined distance from thesecond-conductivity-type second well 35 or overlaps with a portion ofthe second-conductivity-type second well 35. In addition, the pluralityof device isolation films 36 and 37 is formed to locate below the gateG.

Then, a spacer 40 is formed on both sidewalls of the gate G.

As shown in FIG. 4E, a first-conductivity-type bulk pick-up region 41and a plurality of second-conductivity-type source regions 42 are formedin the first-conductivity-type first well 34, and asecond-conductivity-type drain region 43 is formed in thesecond-conductivity-type second well 35. The first-conductivity-typebulk pick-up region 41, the plurality of the second-conductivity-typesource regions 42 and the second-conductivity-type drain region 43 maybe formed by an ion injection process such that the bottoms thereof arehigher than the bottoms of the device isolation films 36 and 37.

Then, interlayer insulating films, metal wirings and the like are formedin a manner similar to a known CMOS process, thereby fabricating asemiconductor device.

In the above embodiments of the present invention, the structurecomprising two device isolation films has been described by a way ofexample. However, two or more device isolation films are also possible,if they can be designed and embodied within a determined space.

In addition, in the above embodiments of the present invention, theapplication of the technical feature of the present invention to alateral double-diffused MOS transistor has been described by way ofexample. However, the technical field of the present invention may beapplied to all types of high-voltage semiconductor devices, includinghigh-voltage MOS transistors, such as lateral double-diffused MOStransistors or EDMOS (extended drain MOS) transistors.

As described above, according to the embodiments of the presentinvention, the breakdown voltage and specific on-resistancecharacteristics of the semiconductor device may be simultaneouslyimproved by forming a plurality of device isolation films between thesource region and the drain region located below the gate.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1-12. (canceled)
 13. A semiconductor device comprising: afirst-conductivity-type substrate; a first-conductivity-type first welland a second-conductivity-type second well formed over thefirst-conductivity-type substrate; a gate formed over thefirst-conductivity-type substrate so as to overlap with thefirst-conductivity-type first well and the second-conductivity-typesecond well; a second-conductivity-type source region formed in thefirst-conductivity-type first well, at one side of the gate; asecond-conductivity-type drain region formed in thesecond-conductivity-type second well, at the other side of the gate; anda plurality of device isolation films formed in thesecond-conductivity-type second well, below the gate.
 14. Thesemiconductor device of claim 13, wherein the first-conductivity-typefirst well and the second-conductivity-type second well that face eachother below the gate, are spaced at a predetermined distance from eachother or come into contact with each other.
 15. The semiconductor deviceof claim 13, wherein the plurality of device isolation films have thesame linewidth or the linewidth thereof decreases gradually inaccordance with the direction from the drain region toward the sourceregion.
 16. The semiconductor device of claim 13, wherein the pluralityof device isolation films have the same depth or the depth thereofdecreases gradually in accordance with the direction from the drainregion toward the source region.
 17. The semiconductor device of claim13, wherein, among the plurality of device isolation films, a deviceisolation film located closest to the drain region is in contact withthe drain region.
 18. The semiconductor device of claim 17, wherein thedevice isolation film located closest to the drain region has thelargest linewidth and depth among the plurality of device isolationfilms.
 19. The semiconductor device of claim 13, wherein the pluralityof device isolation films comprise a structure formed by a shallowtrench isolation (STI) process.